Power semiconductor devices (semiconductor devices with a parallel circuit comprising a plurality of cells, for example MOS (metal oxide semiconductor) transistor cells or bipolar transistor cells for processing high currents/voltages, are generally designed such that they have a lowest possible on resistivity Ron. A (Ron=on resistance, A=cross-sectional area of the semiconductor volume permeated by electric currents) and also a highest possible integration density.
In order to keep the on resistivity as low as possible, it is advisable to use thick metallization layers since it is possible in this way to reduce shunt current resistance components within the metallization layers. However, the use of thick metallization layers has the disadvantage that space-saving wirings and thus high integration densities are not possible within edge regions or logic regions of the power semiconductor device. This problem area shall be explained by way of example below with reference to FIGS. 1 to 3.
FIG. 1 shows a part of an edge section of a power semiconductor device in a cross-sectional illustration. An insulation layer 2 is arranged on a substrate 1, in which a plurality of doped zones are formed (not shown), a patterned metallization layer in turn being arranged on said insulation layer. A first metallization region 3 and also a second metallization region 4 of the metallization layer can be seen in FIG. 1. The pattered metallization layer is coated with a passivation layer 5. A plug P is furthermore provided, which electrically connects the metallization region 4 to a field plate made of polysilicon (not shown here) and thus enables a vertical current flow between the metallization region 4 and the field plate. The field plate serves for potential reduction here.
In order to minimize shunt current resistance components (i.e. resistance components that take effect in the case of a current flow parallel to the semiconductor surface—here into the plane of the drawing) within the metallization regions 3, 4, the metallization regions 3, 4 have thicknesses of approximately 5 μm. The consequence of this is that the patterning process (wet-chemical etching was used in this example) gives rise to non-negligible, undesirable widenings of the metallization regions 3, 4 in the respective lower parts thereof: thus, a width B1 in the upper part of the first metallization region 3 is approximately 12 μm, whereas a width B2 at the base of the first metallization region 3 is approximately 18 μm. A width B3 between the first metallization region 3 and the second metallization region 4 is approximately 12 μm.
The widenings described above, which result on the one hand from the thickness of the metallization regions 3, 4 and on the other hand from the nature of the patterning method, prevent a miniaturization of the power semiconductor device: if the dimensions between the metallization regions 3, 4 are decreased further, then the functionality of the power semiconductor device is no longer ensured even in the case where the fabrication procedure exhibits small process fluctuations.